Senior RTL Design Engineer

Senior RTL Design Engineer: (Company Name - Subscribers only)

Client Information:A premier chip and silicon IP provider. Seeking a motivated full-time Senior RTL Design Engineer to join our PCIe, CXL, AMBA controller IP design team.You’ll be reporting to the PCIe, CXL, AMBA controller IP Design Manager. You’ll contribute to the architecture, design of next generation IPs, targeting the latest developments in PCIe, CXL and AMBA standards.Responsibilities:Contribute to the architecture and micro-architecture of next generation PCIe / CXL / AMBA controller IPImplement these designs in System VerilogCollaborate with the verification team to verify the IPsParticipate in prototyping of the IPs in cutting edge FPGAs Requirements: MINIMUM of 7+ years of experience with RTL DesignRTL coding: Verilog / System VerilogMaster’s degree (Minimal education) in Electrical Engineering, Computer Engineering or equivalent.7+ years of experience with RTL DesignGood English skills, communication skills, and willingness to work with an international team.Knowledge of AMBA AXI or similar bus protocolsAdditional Desirable requirements:FPGA flows : Vivado / QuartusContinuous Integration : Python / Jenkins / GITKnowledge of PCIe / CXLLinux OS knowledgeTHIS ROLE WILL NOT BE PROVIDING VISA SPONSORSHIP. EU CITIZENS ONLY.